1. Field of the Invention
The present invention relates generally to a semiconductor device, and in particular, to a Phase Locked Loop (PLL) and a method of operating the same.
2. Description of the Related Art
In general, a PLL can be used in various semiconductor technology fields, such as semiconductor memory devices, wired/wireless communication systems, phase adjusters, frequency mixers and clock distribution systems. FIG. 1 is a block diagram schematically illustrating a conventional PLL. Referring to FIG. 1, a PLL 10 includes a Phase Frequency Detector (PFD) 11, a charge pump 12, a loop filter 13 and a Voltage Controlled Oscillator (VCO) 14. The operating process of the PLL 10 is described below. First, the PFD 11 compares the phase and frequency of a reference signal FREF with the phase and frequency of an output signal FVCO and outputs an up signal UP or a down signal DN based on the comparison result. The charge pump 12 controls the charge or discharge operation of the loop filter 13 in response to the up or down signal UP or DN. When the loop filter 13 is charged, control voltage Vc output from the loop filter 13 increases. The VCO 14 alters the frequency of the output signal FVCO in response to the control voltage Vc. The PLL 10 performs the above-described operation until the phase difference and frequency difference between the reference signal FREF and the output signal FVCO fall within a predetermined range. Thereafter, when the phase difference and frequency difference between the reference signal FREF and the output signal FVCO fall within the predetermined range, the PLL 10 is locked and the control voltage of the loop filter 13 is maintained at the voltage level which the PLL 10 is locked. In this case, the time that the PLL 10 takes to be locked may vary depending on the current drive capability of the charge pump 13. For example, when the current drive capability of the charge pump 13 increases, the time that the PLL 10 takes to be locked can decreases, but the stability of the PLL 10 decreases. In contrast, when the current drive capability of the charge pump 13 decreases, the PLL 10 can stably operate, but the time that the PLL 10 takes to be locked increases. As a result, it is preferred that the current drive capability of the charge pump 13 be set in consideration of both the time that the PLL 10 takes to be locked and the stability of the PLL 10. Meanwhile, the current drive capability of the charge pump 13 may vary depending on process, voltage and temperature (hereinafter referred to as PVT). As described above, when the current drive capability of the charge pump 13 varies based on PVT, peaking and ringing phenomena occur in the control voltage Vc in the initial locking operation of the PLL 10. Variation in the control voltage Vc based on variation in PVC is described in detail with reference to FIG. 2 below. FIG. 2 is a graph illustrating the waveform of control voltage illustrated in FIG. 1. When a semiconductor device including the PLL 10 enters a standby mode, the PLL 10 is disabled, and then the operation thereof is stopped. Thereafter, the semiconductor device switches to an active mode, the PLL 10 restarts to operate. In this case, the phase difference and frequency difference between the reference signal FREF and the output signal FVCO considerably fall outside the predetermined range. Therefore, the PFD 11 generates the up or down signal UP or DN, and then controls the charge pump 13 such that the loop filter 13 rapidly performs a charge operation. As a result, the control voltage exponentially increases. When the control voltage Vc considerably increases based on the PVT, a peaking phenomenon may occur as indicated in reference character ‘A’. Such a peaking phenomenon acts as a source causing the ringing phenomenon. As a result, in the initial locking operation of the PLL 10, as the increase width of the control voltage Vc increases, the time T that the control voltage Vc takes to have a stable voltage level increases. As described above, the charge pump 12 of the PLL 10 considerably increases the control voltage Vc depending on variation in PVT in the initial locking operation, so that the peaking and ringing phenomena occur, thereby increasing the time that the PLL 10 takes to be locked.